SAB82538 Datasheet, PDF (169/253 Pages) Infineon Technologies AG – ICs for Communications

Channel Configuration Register 1 (READ/WRITE)
Value after RESET: 00_H
7
CCR1
0
0
0 ODS BCR CM2
SAB 82538
SAF 82538
ASYNC Mode
0
CM0 (offset: 2D)
Note: Unused bits have to be set to logical “0”.
ODS…
Output Driver Select
Defines the function of the transmit data pins (T×DA, T×DB)
0… T×D pin is an open drain output.
1… T×D pin is a push-pull output.
BCR…
Bit Clock Rate
This bit is only valid in clock modes not using the DPLL (0, 1, 3b, 4, 7b).
0… selects isochronous operation with a bit clock rate = 1. Data is
sampled once.
1… selects standard asynchronous operation with a bit clock rate = 16.
Data is sampled 3 times around the nominal bit center. The effective
bit value is determined by majority decision. For correct operation,
NRZ data encoding has to be selected.
CM2– CM0… Clock Mode
Selects one of 8 different clock modes:
000 clock mode 0
•
•
•
•
•
•
111 clock mode 7
Note: Clock mode 5 is only specified for version SAB 82538H-10, not for
SAB 82538H.
Semiconductor Group
169