SAB82538 Datasheet, PDF (53/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Non-Auto-Mode (MODE: MDS1, MDS0 = 01)
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical to auto-mode) are
forwarded directly via the RFIFO to the system memory.
The HDLC control field, data in the I-field and an additional status byte are temporarily
stored in the RFIFO. The HDLC control field and additional information can also be read
from special registers (RHCR, RSTA).
In non-auto-mode, all frames with a valid address are treated similarly.
In version 2 upward the address bytes can be masked to allow selective broadcast frame
recognition. For further information see chapter 2.3.4.10.
Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101)
Characteristics: address recognition high byte
Only the high byte of a 2-byte address field will be compared.The address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values in RAH1 and RAH2 registers. The whole frame
excluding the first address byte will be stored in RFIFO. RAL1 contains the second and
RHCR the third byte following the opening flag.
In version 2 and upwards the address bytes can be masked to allow selective broadcast
frame recognition. For further information see chapter 2.3.4.10.
Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100)
Characteristics: no address recognition
No address recognition is performed and each frame will be stored in the RFIFO. RAL1
contains the first and RHCR the second byte following the opening flag.
Extended Transparent Modes 0, 1 (MODE: MDS1, MDS0 = 11)
Characteristics: fully transparent
In extended transparent modes, fully transparent data transmission/reception without
HDLC framing is performed, i.e. without FLAG generation/recognition, CRC generation/
check, or bit-stuffing. This allows user specific protocol variations.
Data transmission is always performed out of the XFIFO. In extended transparent
mode 0 (ADM = 0), data reception is done via the RAL1 register, which always contains
the current data byte assembled at the R×D pin. In extended transparent mode 1
(ADM = 1), the receive data are additionally shifted into the RFIFO.
Semiconductor Group
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