SAB82538 Datasheet, PDF (84/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Clock Mode 1 (Re./Trm. Strobes)
Externally generated, but identical receive and transmit clocks are supplied via RxCLK.
In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK.
These strobe signals work on a per bit basis. The operating mode can be applied in time
division multiplex applications or for adjusting disparate transmit and receive data rates.
Note: In Extended Transparent Mode (HDLC/SDLC), the above mentioned strobe
signals provide byte synchronization (byte alignment).
Clock Mode 2 (Rec. Clock from DPLL)
The BRG is driven by an external clock (R×CLK) and it delivers a reference clock of a
frequency equal to 16 times the nominal bit rate for the DPLL which in turn generates the
receive clock. Depending on the programming of the CCR2 register (bit SSEL), the
transmit clock will be either an external clock signal (T×CLK) or the clock delivered by
the BRG divided by 16. In the latter case, the transmit clock can be output via T×CLK.
Clock Mode 3 (Rec. and Trm. Clock from DPLL)
The BRG is fed with an externally generated clock via R×CLK. Depending on the value
of bit CCR2.SSEL the BRG supplies either the reference clock of frequency equal to
16 times the nominal bit rate for the DPLL, which generates both the receive and
transmit clock, or, the receive and transmit clock directly. This clock can be output via
T×CLK.
Clock Mode 4 (OSC-Direct)
The receive and transmit clocks are directly supplied by the OSC. In addition, this clock
can be output via T×CLK.
Clock Mode 5 (Time-Slots)
This operation mode has been designed for application in time-slot oriented PCM
systems.
Note: Clock mode 5 is only specified for version SAB 82538H-10, but not for version
SAB 82538H.
For correct operation only NRZ coding should be used
The receive and transmit clocks are common and must be supplied externally via RxCLK
pin. The ESCC8 receives and transmits only during certain time-slots
– of programmable width (1…256 bit, via RCCR and XCCR registers), and
of programmable location with respect to a frame synchronization signal (via CD pin).
One of up to 64 time-slots can be programmed independently for receive and transmit
direction via TSAR and TSAX registers, and an additional clock shift of 0…7 bits via
TSAR, TSAX and CCR2 register. Together with bits XCS0 and RCS0 (LSB of clock
shift), located in the CCR2 register, there are 9 bits to determine the location of a time-
slot.
Semiconductor Group
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