SAB82538 Datasheet, PDF (125/253 Pages) Infineon Technologies AG – ICs for Communications

Receive Address Byte High Register 2 (WRITE)
7
RAH2
RAH2
SAB 82538
SAF 82538
HDLC Mode
MCS
0
0 (offset: 27)
RAH2…
MCS…
Value of second individual high address byte.
Modulo Count Select (valid in auto-mode only!)
The MCS bit determines the HDLC control field format.
0… basic operation, one-byte control field (modulo 8)
1… extended operation, two-byte control field (modulo 128)
Note: When modulo 128 is selected, in auto mode the “RHCR'” register
contains compressed information of the extended control field (see
RHCR register description). RAH1, RAH2 registers are used in auto-
and non-auto operating modes when a 2-byte address field has
been selected (MODE.ADM = 1) and in transparent mode 0.
Receive Address Byte Low Register 1 (WRITE or READ)
7
RAL1
RAL1
0
(offset: 28)
The general function (WRITE or READ) and the meaning or contents of this register
depend on the selected operating mode:
q Auto-/Non-Auto-Mode (16-bit Address) - WRITE Access only:
(Read access not specified)
RAL1 can be programmed with the value of the first individual low address byte.
q Auto-/Non-Auto-Mode (8-bit Address) - WRITE Access only:
(Read access not specified)
According to X.25 LAPB protocol, the address in RAL1 is considered as the address
of a COMMAND frame.
q Transparent Mode 1 (High Byte Address Recognition) - READ Access only:
(Write access has no influence)
RAL1 contains the byte following the high byte of the address in the receive frame (i.e.
the second byte after the opening flag).
q Transparent Mode 0 (No Address Recognition) - READ Access only:
(Write access has no influence)
RAL1 contains the first byte after the opening flag (first byte of received frame).
Semiconductor Group
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