SAB82538 Datasheet, PDF (182/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Interrupt Status Register 1 (READ)
Value after RESET: 00_H
7
ASYNC Mode
0
ISR1
BRK BRKT ALLS XOFF TIN CSC XON XPR (offset: 3B)
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC.VIS is set “1”, interrupt statuses in ISR1 may be flagged although they
are masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
BRK…
Break
This bit is set when a Break signal - static low level for a time equal to
(character length + parity + stop bit(s)) – is detected on R×D.
BRKT…
Break Terminated
This bit is set when a Break signal on R×D is terminated.
ALLS…
All Sent
This bit is set when the XFIFO is empty and the last character is completely
sent out on T×D.
XOFF…
XOFF Character Detected
This interrupt status indicates that the currently received character matches
the value specified via register XOFF. The function is independent of the
programming of bit MODE.FLON.
TIN…
Timer Interrupt
The internal timer has expired (see also description of TIMR register).
CSC…
Clear To Send Status Change
Indicates that a state transition has occurred on CTS. The actual state of
CTS can be read from STAR register (CTS bit).
XON…
XON Character Detected
This interrupt status indicates that the currently received character matches
the value specified via register XON. The function is independent of the
programming of bit MODE.FLON.
XPR…
Transmit Pool Ready
A data block of up to 32 bytes can be written to XFIFO.
Semiconductor Group
182