SAB82538 Datasheet, PDF (144/253 Pages) Infineon Technologies AG – ICs for Communications

RSC…
PCE…
PLLA…
CDSC…
RFO…
RPF…
SAB 82538
SAF 82538
HDLC Mode
Receive Status Change (significant in auto-mode only)
A status change (receiver ready/receiver not ready) of the remote station
has been detected by receiving a RR/RNR supervisory frame. The actual
status can be read from the STAR register (RRNR bit).
Protocol Error (significant in auto-mode only)
The ESCC8 has detected a protocol error, i.e. it has received
– an S- or I-frame with incorrect N (R)
– an S-frame containing an I-field.
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the DPLL and
FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is disabled
(receiver aborted) until synchronization has been regained. Additionally,
transmission is also interrupted if the transmit clock is derived from the
DPLL.
Carrier Detect Status Change
Indicates that a state transition has occurred on CD. The actual state can
be read from the VSTR register.
Receive Frame Overflow
At least one complete frame was lost because no storage space was
available in the RFIFO. This interrupt can be used for statistical purposes
and indicates that the CPU does not respond quickly enough to an RPF or
RME interrupt.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not yet
completely received.
Note: This interrupt is only generated in Interrupt Mode.
Semiconductor Group
144