SAB82538 Datasheet, PDF (242/253 Pages) Infineon Technologies AG – ICs for Communications

5.4.3.2 Receive Cycle Timing
SAB 82538
SAF 82538
Figure 67
Receive Cycle Timing
Note 1: Whichever supplies the clock: externally clocked by R×CLK or XTAL1, or,
internally derived from DPLL, BRG or BCR divider (refer to table 5)
Note 2: NRZ, NRZI and Manchester coding
Note 3: FM0 and FM1 coding
Note 4: Carrier detect auto start enabled (not for clock modes 1, 5)
Semiconductor Group
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