SAB82538 Datasheet, PDF (136/253 Pages) Infineon Technologies AG – ICs for Communications

PSD…
SAB 82538
SAF 82538
HDLC Mode
DPLL Phase Shift Disable
Only applicable in the case of NRZ and NRZI encoding.
If this bit is set to “1”, the Phase Shift function of the DPLL is disabled. In
this case the windows for Phase Adjustment are extended.
Time-Slot Assignment Register Transmit (WRITE)
This register is only used in clock mode 5!
Value after RESET: 00_H
7
TSAX
TSNX
0
XCS2 XCS1 (offset: 30)
TSNX…
Time-Slot Number Transmit
Selects one of up 64 possible timeslots (00_H–3F_H) in which data is
transmitted. The number of bits per timeslot can be programmed via XCCR.
XCS2, XCS1… Transmit Clock Shift, Bit 2-1
Together with bit XCS0 in CCR2, transmit clock shift can be adjusted.
Time-Slot Assignment Register Receive (WRITE)
This register is only used in clock mode 5!
Value after RESET: 00_H
7
TSAR
TSNR
0
RCS2 RCS1 (offset: 31)
TSNR…
Time-Slot Number Receive
Defines one of up to 64 possible time-slots (00_H-3F_H) in which data is
received. The number of bits per time-slot can be programmed via RCCR.
RCS2, RCS1… Receive Clock Shift, Bit 2-1
Together with bit RCS0 in CCR2, the receive clock shift can be adjusted.
Semiconductor Group
136