SAB82538 Datasheet, PDF (137/253 Pages) Infineon Technologies AG – ICs for Communications

Transmit Channel Capacity Register (WRITE)
This register is only used in clock mode 5!
Value after RESET: 00_H
7
XCCR XBC7
SAB 82538
SAF 82538
HDLC Mode
0
XBC0 (offset: 32)
XBC7 – XBC0… Transmit Bit Number Count, Bit 7-0
Defines the number of bits to be transmitted within a time-slot:
Number of bits = XBC + 1 (1 … 256 bits/time-slot).
Receive Channel Capacity Register (WRITE)
This register is only used in clock mode 5!
Value after RESET: 00_H
7
RCCR RBC7
0
RBC0 (offset: 33)
RBC7 – RBC0… Receive Bit Count, Bit 7-0
Defines the number of bits to be received within a time-slot:
Number of bits = RBC + 1 (1 … 256 bits/time-slot).
Version Status Register (READ)
7
VSTR
CD DPLA 0
0 VN3
0
VN0 (offset: 34)
CD…
DPLA…
Carrier Detect
This bit reflects the state of the CD pin.
1… CD active
0… CD inactive
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the DPLL and
FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is disabled
(receiver aborted) until synchronization has been regained. Additionally,
transmission is interrupted, too, if the transmit clock is derived from the
DPLL (same effect as the deactivation of pin CTS).
Semiconductor Group
137