SAB82538 Datasheet, PDF (71/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.3.4.8 One Bit Insertion
Similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the HDLC
protocol, the ESCC8 offers a completely new feature of inserting/deleting a one after
seven consecutive zeros in the transmit/receive data stream, if the serial channel is
operating in a bus configuration. This method is useful if clock recovery is to be
performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive “0”-s
received, and the DPLL may lose synchronization.
Using the one bit insertion feature by setting the OIN bit in the CCR1 register, however,
it is guaranteed that at least after
– 5 consecutive “1”-s a “0” will appear (bit-stuffing), and after
– 7 consecutive “0”-s a “1” will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit-stuffing, the “one insertion” is fully transparent to the user, but it is
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implement this function, such as the SAB 82532.
2.3.4.9 CRC ON/OFF Feature (version 2 upward)
As an option in non-auto mode or transparent mode 0, the internal handling of received
and transmitted CRC checksum can be influenced via control bits CCR3.RCRC and
CCR3.XCRC.
Receive Direction
The received CRC checksum is always assumed to be in the 2 (CRC-CCITT) or 4
(CRC-32) last bytes of a frame, immediately preceding a closing flag. In the version 1 of
ESCC8 a check is performed on the CRC but the received CRC bytes are not transferred
to the RFIFO. In version 2 upwards, if CCR3.RCRC is set, the received CRC checksum
will be written to RFIFO where it precedes the frame status byte (contents of register
RSTA). The received CRC checksum is additionally checked for correctness. If non-auto
mode is selected, the limits for “Valid Frame” check are modified (refer to description of
bit RSTA.VFR).
Transmit Direction
If CCR3.XCRC is set, the CRC checksum is not generated internally. The checksum has
to be provided via the transmit FIFO (XFIFO) as the last two or four bytes. The
transmitted frame will only be closed automatically with a (closing) flag.
Note: The ESCC8 does not check whether the length of the frame, i.e. the number of
bytes to be transmitted makes sense or not.
Semiconductor Group
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