SAB82538 Datasheet, PDF (52/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.3 HDLC/SDLC Serial Mode
2.3.1 Operating Modes
The HDLC controller of each channel can be programmed to operate in various modes,
which are different in the treatment of the HDLC frame in receive direction. Thus, the
receive data flow and the address recognition features can be performed in a very
flexible way, to satisfy almost any practical requirements.
There are 6 different operating modes which can be set via the MODE register.
Auto-Mode (MODE: MDS1, MDS0 = 00)
Characteristics: Window size 1, random message length, address recognition.
The ESCC8 processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, data in the I-field of the frames and an additional status
byte are temporarily stored in the RFIFO. The HDLC control field as well as additional
information can also be read from special registers (RHCR, RSTA).
Depending on the selected address mode, the ESCC8 can perform a 2-byte or 1-byte
address recognition. If a 2-byte address field is selected, the high address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values in RAH1 and RAH2 registers. According to the ISDN
LAPD protocol, bit 1 of the high byte address will be interpreted as COMMAND/
RESPONSE bit (C/R), dependent on the setting of the CRI bit in RAH1, and will be
excluded from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the ESCC8 can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through the address combination RAH1, RAL1 will be processed
in the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match any of the address combinations, are ignored by the ESCC8.
In the case of a 1-byte address, RAL1 and RAL2 will be used as comparison registers.
According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as
COMMAND and the value in RAL2 as RESPONSE.
In version 2 and upwards the address bytes can be masked to allow selective broadcast
frame recognition. For further information see chapter 2.3.4.10.
Semiconductor Group
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