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SAB82538 Datasheet, PDF (197/253 Pages) Infineon Technologies AG – ICs for Communications | |||
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Data Format (READ/WRITE)
Value after RESET: 00H
7
DAFO
0
0
0
SAB 82538
SAF 82538
BISYNC Mode
0
PAR1 PAR0 PARE CHL1 CHL0 (offset: 27)
Note: Unused bits have to be set to logical â0â.
PAR1, PAR0⦠Parity Format
If parity check/generation is enabled by setting PARE, these bits define the
parity type:
00⦠SPACE (â0â)
01⦠odd parity
10⦠even parity
11⦠MARK (â1â)
The received parity bit is stored in RFIFO
â as leading bit immediately preceding the character if character length is
5 to 7 bits and RFC.DPS is set to 0, and as LSB of the status byte
pertaining to the character if the corresponding RFIFO data format is
enabled.
â as LSB of the status byte pertaining to the character if character length is
8 bits and the corresponding RFIFO data format is enabled.
Parity error is indicated in the MSB of the status byte pertaining to the
character, if enabled. Additionally, a parity error interrupt can be generated.
PAREâ¦
Parity Enable
0⦠parity check/generation disabled
1⦠parity check/generation enabled
CHL1âCHL0⦠Character Length
These bits define the length of received and transmitted characters,
excluding optional parity:
00⦠8 bit
01⦠7 bit
10⦠6 bit
11⦠5 bit
Semiconductor Group
197
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