SAB82538 Datasheet, PDF(181/253 Page) Infineon Technologies AG – ICs for Communications

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SAB82538 Datasheet, PDF (181/253 Pages) Infineon Technologies AG – ICs for Communications

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PLLAâ¦

CDSCâ¦

RFOâ¦

RPFâ¦

SAB 82538

SAF 82538

ASYNC Mode

DPLL Asynchronous

This bit is only valid when the receive clock is supplied by the DPLL and

FM0, FM1 or Manchester data encoding is selected.

It is set when the DPLL has lost synchronization. Reception is disabled

(IDLE is inserted) until synchronization has been regained. Additionally,

transmission is also interrupted if the transmit clock is derived from the

DPLL.

Carrier Detect Status Change

Indicates that a state transition has occurred on CD. The actual state of CD

can be read from the VSTR register.

Receive FIFO Overflow

This interrupt is generated if RFIFO is full and a further character is

received. This interrupt can be used for statistical purposes and indicates

that the CPU does not respond quickly enough to an RPF or TCD interrupt.

Receive Pool Full

This bit is set if RFIFO is filled with data (character and optional status

information) up to the programmed threshold level.

Note: This interrupt is only generated in Interrupt Mode.

Semiconductor Group

181

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