SAB82538 Datasheet, PDF (238/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Motorola Bus Interface Timing and Interrupt Timing (cont’d)
Parameter
No. Symbol
INTA control interval
22A t_rec(INTA)
INT reset after last INTA inactive
23
t_INTA-INT
Slave address (IE0, IE1, IE2) setup time
24 t_su(IE)
Slave address (IE0, IE1, IE2) hold time
25 t_h(IE)
IE0 low after IE1 low
28
t_IE1L-IE0L
IE0 high after IE1high
29
t_IE1H-IE0H
IE0 low after INT active
30
t_INTV-IE0L
INT inactive after IE1 low
31
t_dis(INT)
INT reactivated after IE1 high
32
t_IE1H-INTV
IE0 high after INT reset
33
t_INT-IE0H
INTA setup time
48
t_su(INTA)
INTA hold time
48A t_h(INTA)
Interrupt vector hold after DS or INTA inactive 49 t_v(VEC)
DTACK active delay
50 t_p(DTK)
DTACK active to data valid (read cycle)
50A t_DTK-D
DTACK hold after command inactive
52 t_v(DTK)
DTACK high to DTACK high impedance
52A t_h(DTK)
W to R control interval
95 t₉₅
Limit Values Unit
min. max.
30
ns
60 ns
10
ns
30
ns
20 ns
20 ns
10 ns
25 ns
25 ns
30 ns
0
ns
0
ns
10 40 ns
60 ns
45 ns
10
ns
40 ns
100
ns
Note: 49max, 50A and 52A are not tested in production.
95 tbd in 5.95
Semiconductor Group
238