SAB82538 Datasheet, PDF (100/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
3
Operational Description
3.1 Reset
The ESCC8 is forced into the reset state if the RES pin is set “high” for at least
5 microseconds. During RESET, the ESCC8 is temporarily in the power-up mode, and
a subset of the registers is initialized with defined values.
During hardware reset
– all uni-directional output stages are in high-impedance state.
– all bi-directional output stages (data bus) are in high-impedance state if signals RD
and INTA are “high”,
– “output” XTAL2 is high-impedance if input XTAL1 is “high” (the internal oscillator is
disabled during reset).
After RESET, the ESCC8 is in power-down mode, and the following registers contain
defined values:
Register
CCR0
CCR1
CCR2
CCR3
Reset Value
00_H
00_H
00_H
00_H
Meaning
– Power down mode
– HDLC/SDLC mode
– NRZ coding
– No Shared Flags
– No SDLC Loop function
– T×D pins are open drain outputs
– pt – pt with IDLE as Interframe Time Fill
– Clock mode 0
– RTS pin standard function
– READ/WRITE Exchange disabled
– CRC-32 disabled
– No data inversion
– No Preambles
– CRC reset level is “FFFF”_H– No ADDRESS to
RFIFO
– No CRC-Bytes to RFIFO
– Transmit CRC OFF
Semiconductor Group
100