SAB82538 Datasheet, PDF (230/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Siemens/Intel Bus Interface and Interrupt Timing (cont’d)
Parameter
No. Symbol
Data hold after WR inactive
16
DRT low after CS, DACK active
17
DRT return to one after CS, DACK inactive 18
CS, DACK inactive setup (INTA cycle) 19
CS, DACK inactive hold (INTA cycle)
20
INTA pulse width
21
INTA control interval
22
INT reset after last INTA inactive
23
Slave address (IE0, IE1, IE2) setup time 24
Slave address (IE0, IE1, IE2) hold time 25
Interrupt vector (D7-D0) valid after INTA 26
active
t_h(D)
t_dis(DRT)
t_p(DRT)
t_dis(S-INT)
t_INTA-S
t_w(INTA)
t_rec(INTA)
t_INTA-INT
t_su(IE)
t_h(IE)
t_a(VEC)
Interrupt vector (D7-D0) hold after INTA 27 t_v(VEC)
inactive
Interrupt vector (D7-D0) hold after INTA 27A t_h(VEC)
inactive
IE0 low after IE1 low
t 28
IE1L-IE0L
IE0 high after IE1 high
t 29
IE1H-IE0H
IE0 low after INT active
t 30
INTV-IE0L
INT inactive after IE1 low
t 31
dis(INT)
Note: 27A and 52A are not tested in production
Limit Values Unit
min. max.
10
ns
50
ns
60
ns
0
ns
0
ns
75
ns
30
ns
60
ns
10
ns
30
ns
50
ns
10
ns
40
ns
20
ns
20
ns
10
ns
25
ns
Semiconductor Group
230