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| SAB82538 Datasheet, PDF (176/253 Pages) Infineon Technologies AG – ICs for Communications | |||
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SAB 82538
SAF 82538
Global Interrupt Status Register (READ)
Value after RESET: 00H
7
ASYNC Mode
0
GIS
PIA PIB PIC PID CII CN2 CN1 CN0 (038/078/0B8/0F8)
(138/178/1B8/1F8)
This status register points to pending
â channel assigned interrupts (ISR0_x, ISR1_x)
â universal port interrupts (PISAâ¦D).
GIS is accessible via eight channel addresses (038H to 1F8H).
PIAâ PID⦠Port Interrupt Indication
These status bits point to pending interrupts in corresponding Port Interrupt
Status registers PISAâ¦PISD. They may be set independently from channel
assigned interrupts.
CIIâ¦
Channel Interrupt Indication
Set if at least one interrupt source of any channel is active.
CN2â CN0⦠Channel Number (0â¦7)
If at least one interrupt source is active (bit CII is set), these bits point to the
channel with currently highest source priority. Refer to chapter 2.2.3 for
detailed description of the priority structure.
Contents of register GIS are frozen after every input acknowledge cycle.
â after the first read access to GIS after the interrupt vector has been output,
â after every read access to anyone of the channel assigned interrupt status registers,
â during every INTA cycle.
Semiconductor Group
176
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