SAB82538 Datasheet, PDF (245/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Note 1: Whichever supplies the clock: externally clocked by TxCLK, XTAL1 or RxCLK
or, internally derived from DPLL, BRG or BCR divider (refer to table 5).
Note 2: NRZ and NRZI coding.
Note 3: FM0, FM1 and Manchester coding.
Note 4: If output function is enabled (refer to table 5).
Note 5: The timing shown is valid for normal operation and bus configuration mode 1.
In bus configuration mode 2, RTS and TxD are shifted for 1/2 Xclock period.
Semiconductor Group
245