SAB82538 Datasheet, PDF (171/253 Pages) Infineon Technologies AG – ICs for Communications

BDF...
SSEL...
TOE...
RWX...
DIV...
SAB 82538
SAF 82538
ASYNC Mode
Baud Rate Division Factor
0…The division factor of the baud rate generator is set to 1 (constant).
1…The division factor is determined by BR9 - BR0 bits in CCR2 and BRG
registers.
Clock Source Select
Selects the clock source in clock modes 0, 2, 3, 6 and 7 (refer to table 5).
T×CLK Output Enable
0… T×CLK pin is input
1… T×CLK pin is switched to output function if applicable to the selected
clock mode (refer to table 5).
Read/Write Exchange
Valid only in DMA mode. If this bit is set, the
– RD and WR pins are internally exchanged (Siemens/Intel bus interface)
– R/W pin is inverted in polarity (Motorola bus interface)
while any DACK input is active. This useful feature allows a simple
interfacing to the DMA controller.
Note: The RWX bit of all eight channels is “or”ed.
Data Inversion
Only valid if NRZ data encoding is selected. Data is transmitted and
received inverted.
Channel Configuration Register 3 (READ/WRITE)
(Version 2 upwards)
Value after RESET: 00_H
7
CCR3
0
0
0
0
0
0
0
0 PSD (offset: 2F)
Note: Unused bits have to be set to logical “0”.
PSD…
DPLL Phase Shift Disable
Only applicable in the case of NRZ and NRZI encoding.
If this bit is set to “1”, the Phase Shift function of the DPLL is disabled. In
this case the windows for Phase Adjustment are extended.
Semiconductor Group
171