SAB82538 Datasheet, PDF (47/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Subsequent actions depend on the indicated interrupt group (similar to vector
mode 1):
If one of interrupt groups 0 to 2 is indicated, no reading of channel assigned interrupt
status registers is necessary; the corresponding interrupt indication is reset after the
INTA cycle has been finished.
If interrupt group 3 is indicated, the interrupt status registers ISR0_x and ISR1_x
which correspond to the requesting channel have to be examined. Version 1: in case
channel 7 is indicated the global status register GIS has to be evaluated for pending
channel and/or universal port interrupts. Version 2 upward: the “PI”-bit indicates a
pending parallel port interrupt separately from channel 7 interrupts.
The INT signal is reset when all interrupt indications are cleared (acknowledged). See
also exceptions in Daisy Chaining mode.
Note: Contents of Global Interrupt Status register GIS are frozen after every interrupt
acknowledge cycle. Updating starts
– after the first read access to GIS after the interrupt vector has been output,
– after every read access to anyone of the channel assigned interrupt status
registers,
– during every INTA cycle.
Updating of channel assigned interrupt status registers ISR0_x and ISR1_x is only
prohibited during read access. Thus, status information may include indications of higher
priority even in case of group 3 interrupts (e.g. a timer interrupt TIN channel 5 triggers
an interrupt vector generation with group 3, channel 5 indication; before the service
routine is able to read ISR0_5 and ISR1_5, an RPF condition occurs for channel 5; the
current status information now includes TIN and RPF indication). This is implemented to
avoid wasting time with servicing of low level requests while an urgent request of that
channel is pending. This must be taken into consideration when designing the interrupt
service routine for group 3 interrupts.
Masked Interrupts Visible in Status Registers (Version 2 Upward)
The interrupt vector contains only one interrupt at a time: the interrupt displayed in this
vector results from a priority resolution among all unmasked active interrupt statuses.
The Global Interrupt Status register (GIS) points to interrupt status registers with active
interrupt indications. Register GIS should be evaluated if a pure interrupt polling scheme
is used.
In version 1 of ESCC8 only unmasked interrupt statuses may:
– generate an interrupt at pin INT,
– generate an interrupt vector,
– be visible in GIS, and
– be visible in the interrupt status registers ISR0_0..7, ISR1_0..7 and PISA..D.
Semiconductor Group
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