SAB82538 Datasheet, PDF (50/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.2.5 FIFO Structure
In all transmit and receive direction 64-byte deep FIFOs are provided for the
intermediate storage of data between the serial interface and the CPU interface. The
FIFOs are divided into two halves of 32-bytes. Only one half is accessible to the CPU or
DMA controller at any time.
Organization of the FIFOs and access to their contents depends on the selected serial
mode. For detailed information, refer to description of RFIFO and XFIFO in chapter 4.1,
chapter 4.2 and chapter 4.3. In case 16-bit data bus width is selected by fixing pin
WIDTH to logical “1” word access to the FIFOs is enabled. Data output to bus lines D0-
D15 as a function of the selected interface mode is shown in figure 17 and 18. Of
course, byte access is also allowed.
The effective length of the accessible part of RFIFO can be changed from 32 bytes
(RESET value) down to 1 (ASYNC and BISYNC mode) or 2 (HDLC mode) bytes.
In version 1, only threshold 32 is available in HDLC mode.
Figure 17
FIFO Word Access (Intel Mode)
Semiconductor Group
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