SAB82538 Datasheet, PDF (63/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
After the frame has been transmitted (with the final bit set), the XFIFO is inhibited and
the ESCC8 waits for the arrival of a positive acknowledgement.
Since the on-chip timer of the ESCC8 must be operated in the external mode (a
secondary may not poll the primary for acknowledgements), timer supervision must be
done by the primary station.
Upon the arrival of an acknowledgement the XFIFO is enabled and an interrupt is
forwarded to the CPU, either the
– message has been positively acknowledged (ALLS interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the timer can be used under CPU control to provide timer recovery of the
secondary if no acknowledgements are received at all.
Note: The transmission of transparent frames is possible only if the permission to send
is given by an S-frame (p = 1) or I-frame.
Examples
A few examples of ESCC8 / CPU interaction in the case of NRM mode are shown in
figure 27 to 30.
Figure 27
No Data to Send
Semiconductor Group
63