SAB82538 Datasheet, PDF (117/253 Pages) Infineon Technologies AG – ICs for Communications

STI…
XTF…
XIF…
XME…
XRES…
SAB 82538
SAF 82538
HDLC Mode
If XREP is set to one together with XTF and XME (write 2AH to CMDR), the
ESCC8 repeatedly transmits the contents of the XFIFO (1… 32 bytes)
without HDLC framing fully transparently, i.e. without FLAG, CRC or Bit
Stuffing.
The cyclic transmission is stopped with an XRES command.
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after start.
Transmit Transparent Frame
• Interrupt Mode
After having written up to 32 bytes to the XFIFO, this command initiates the
transmission of a transparent frame. An opening flag sequence is
automatically added to the data by the ESCC8.
• DMA Mode
After having written the length of the frame to be transmitted to the XBCH,
XBCL registers, this command initiates the data transfer from system
memory to ESCC8 by DMA. Serial data transmission starts as soon as 32
bytes are stored in the XFIFO or the Transmit Byte Counter value is
reached.
Transmit I-Frame (used in auto-mode only!)
Initiates the transmission of an I-frame in auto-mode. Additionally to the
opening flag sequence, the address and control field of the frame is
automatically added by ESCC8.
Transmit Message End (used in interrupt mode only!)
Indicates that the data block written last to the transmit FIFO completes the
current frame. The ESCC8 can terminate the transmission operation
properly by appending the CRC and the closing flag sequence to the data.
In DMA Mode, the end of the frame is determined by the Transmit Byte
Count in XBCH, XBCL, thus, XME is not used in this case.
Transmitter Reset
XFIFO is cleared of any data and an abort sequence (seven 1's) followed
by interframe time fill is transmitted. In response to XRES an XPR interrupt
is generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Semiconductor Group
117