SAB82538 Datasheet, PDF (146/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
This bit is set
– if the last bit of the current frame is completely sent out on T × D and
XFIFO is empty (non-auto mode, transparent modes).
– if an I-Frame is completely sent out on T × D and a positive
acknowledgment has been received (auto mode).
– In auto-mode, if an I-frame has been sent and a timer interrupt (TIN) is
generated because the internal timer expires before an acknowledgment
is received: in this case ALLS is generated one clock period after (TIN).
XDU/EXE... Transmit Data Underrun/Extended Transmission End
Transmitted frame was terminated with an abort sequence because no
data was available for transmission in XFIFO and no XME was issued
(interrupt mode) or DMA request was not satisfied in time (DMA mode).
Note: Transmitter and XFIFO are reset and deactivated if this condition
occurs. They are re-activated not before this interrupt status register
has been read. Thus, XDU should not be masked via register IMR1.
In extended transparent mode, this bit indicates the transmission-end
condition (EXE).
TIN...
Timer Interrupt
The internal timer and repeat counter has expired (see also description of
TIMR register).
CSC...
Clear To Send Status Change
Indicates that a state transition has occurred on CTS. The actual state can
be read from STAR register (CTS bit).
XMR...
Transmit Message Repeat
The transmission of the last frame has to be repeated because
– the ESCC8 has received a negative acknowledgment to an I-frame in
auto-mode, or
– a collision has occurred after at least one FIFO block of data has been
completely transmitted, and thus an automatic re-transmission cannot be
attempted, or
– CTS (transmission enable) has been withdrawn after at least one FIFO
block of data has been transmitted and the frame has not been
completed.
Note: For easier recovery in the case of a collision, XFIFO should not
contain data of more than one frame.
The use of ALLS interrupt is therefore recommended.
Semiconductor Group
146