SAB82538 Datasheet, PDF (88/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
The following functions have been implemented to facilitate a fast and reliable
synchronization:
– Interference Rejection and Spike Filtering
In the case where two or more edges appear in the data stream within a time period of
16 reference clocks, these are considered as interference and consequently no
additional clock adjustment is performed.
– Phase Adjustment
In the case where an edge appears in the data stream within the PA fields of the time
window, the phase will be adjusted by 1/16 of the data clock.
– Phase Shift (NRZ, NRZI only)
In the case where an edge appears in the data stream within the PS fields of the time
window, a second sampling of the bit is forced and the phase is shifted by 180 degrees.
– Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications. Above all, it implies a very fast synchronization because of the phase shift
feature: one edge on the received data stream is enough for the DPLL to synchronize,
thereby eliminating the need for synchronization patterns sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of
the clock recovery cannot be guaranteed.
The version 2 of ESCC8 offers the option to disable the Phase Shift function for NRZ and
NRZI encodings by setting bit CCR3.PSD. In this case, the PA fields are extended as
shown in figure .
Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach
the optimal sampling position. To ensure correct data sampling preambles should
precede the data information.
Figures 36, and 38 explain the DPLL algorithms used for the different data encodings.
Semiconductor Group
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