SAB82538 Datasheet, PDF (113/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
Table 9
Register Addresses in HDLC Mode (cont’d)
Address (A8… A0)
Channel
0
1
2
3
4
5
6
7
036 076 0B6 0F6 136 176 1B6 1F6
037 077 0B7 0F7 137 177 1B7 1F7
038, 078, 0B8, 0F8, 138, 178, 1B8, 1F8
039, 079, 0B9, 0F9, 139, 179, 1B9, 1F9
03A 07A 0BA 0FA 13A 17A 1BA 1FA
03B 07B 0BB 0FB 13B 17B 1BB 1FB
03C, 07C 0BC, 0FC 13C, 17C 1BC, 1FC
03D, 07D 0BD, 0FD 13D, 17D 1BD, 1FD
03E, 07E 0BE, 0FE 13E, 17E 1BE, 1FE
03F 07F 0BF 0FF 13F 17F 1BF 1FF
Register
Read
Write
———
AML
———
AMH
GIS *)
IVA *)
IPC *)
ISR0
IMR0
ISR1
IMR1
PVRA…D
PISA..D
PIMA..D
PCRA…D
CCR4
*) All channel assigned addresses enable access to the same register(s)
Note: Read access to unused register addresses: value should be ignored,
Write access to unused register addresses: should be avoided, or set to '00'hex.
4.1.2 Register Definitions
Receive FIFO (READ) RFIFO (offset: 00…1F)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) access
depending on the selected bus interface mode. The LSB is received first from the serial
interface.
In Versions 2 and upwards, the size of the accessible part of RFIFO is determined by
programming the bits CCR4.RFT 1 … 0 (RFIFO threshold level). It can be reduced from
32 bytes (RESET value) down to 2 bytes (four values: 32, 16, 4, 2 bytes).
q Interrupt Controlled Data Transfer (Interrupt Mode)
Selected if DMA bit in XBCH is reset.
Up to 32 bytes/16 words of received data can be read from the RFIFO following an
RPF
or an RME interrupt.
RPF Interrupt: A fixed number of bytes/words to be read (version 1:32 bytes; version
2 upward: 32,16,4,2 bytes). The message is not yet complete.
RME Interrupt: The message is completely received. The Number of valid bytes is
determined by reading the RBCL, RBCH registers.
RFIFO is released by issuing the “Receive Message Complete” command (RMC).
Semiconductor Group
113