SAB82538 Datasheet, PDF (121/253 Pages) Infineon Technologies AG – ICs for Communications

TMD…
RAC…
RTS…
TRS…
TLP…
SAB 82538
SAF 82538
HDLC Mode
Timer Mode
Determines the operating mode of the timer.
0… external mode
The timer is controlled by the CPU and can be started at any time by setting
the STI bit in CMDR.
1… internal mode
The timer is used internally by the ESCC8 for time-out and retry conditions
in auto-mode (refer to the description of the TIMR register).
Receiver Active
Switches the receiver to operational or inoperational state.
0… receiver inactive
1… receiver active
In extended transparent modes this bit must be reset to enable fully
transparent reception.
Request To Send
Defines the state and control of RTS pin.
0… The RTS pin is controlled by the ESCC8 autonomously.
RTS is activated when a frame transmission starts and deactivated
when transmission is completed.
1… The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active
till this bit is reset.
Timer Resolution
Selects the resolution of the internal timer (factor k, see description of TIMR
register):
0… k = 32 768
1… k = 512
Test Loop
Input and output of the HDLC channel are internally connected.
(e.g. transmitter channel 0 - receiver channel 0)
Semiconductor Group
121