SAB82538 Datasheet, PDF (158/253 Pages) Infineon Technologies AG – ICs for Communications

Command Register (WRITE)
Value after RESET: 00_H
7
CMDR RMC RRES RFRD STI XF 0
SAB 82538
SAF 82538
ASYNC Mode
0
0 XRES (offset: 20)
Note: Unused bits have to be set to logical “0”.
The maximum time between writing to the CMDR register and the execution of
the command is 2.5 clock cycles. Therefore, if the CPU operates with a very high
clock rate in comparison with the ESCC8’s clock, it is recommended that the CEC
bit of the STAR register be checked before writing to the CMDR register to avoid
any loss of commands.
RMC…
Receive Message Complete
Confirmation from CPU to ESCC8 that the current data block has been
fetched following a RPF or TCD interrupt or following a user initiated read
access in conjunction with the RFIFO Read command RFRD; the occupied
space in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after a TCD interrupt
in order to enable the generation of further receiver DMA requests.
RRES…
Receiver Reset
All data in RFIFO and ASYNC receiver is deleted.
RFRD…
Receive FIFO Read Enable
The CPU can have access to RFIFO by issuing the RFRD command before
threshold level or the end condition (TCD) are fulfilled. After issuing the
RFRD command the CPU has to wait for TCD interrupt, before reading
RBC and RFIFO. The number of valid bytes is determined by reading the
RBCL register.
STI…
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after start.
XF…
Transmit Frame
q Interrupt Mode
After having written up to 32 bytes/16 words to the XFIFO, this command
initiates the transmission of data.
q DMA Mode
After having written the amount of data to be transmitted to the XBCH,
XBCL registers, this command initiates the data transfer from system
Semiconductor Group
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