SAB82538 Datasheet, PDF (101/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Register
MODE
IMR0
IMR1
PIM
IPC
PCR
IVA
PRE
XBCH
STAR
AML/MXN
AMH/MXF
TSAX
TSAR
XCCR
RCCR
Reset Value
00_H
FF_H
FF_H
FF_H
00_H
FF_H
00_H
00_H
00_H
48_H
00_H
00_H
00_H
00_H
Meaning
– Auto/mode with 1 byte address field
– External timer mode, timer resolution: k = 32768
– Receiver active
– RTS output controlled by ESCC8
– No test loop
– All interrupts masked
– Interrupt pin INT is an open drain output
– Slave Cascading mode is enabled
– Slave address is set to 00_H
– All pins of the Universal Port are inputs
– Interrupt vector address is set to 00_H
– Preamble value is set to 00_H
– Interrupt controlled data transfer (DMA disabled)
– Full/duplex LAPB/LAPD operation of LAP controller
– Carrier detect auto start of receiver disabled
– XFIFO write enabled
– Receive line inactive
– No commands executing
– Address mask disabled
– Time-slot number: 00_H
– Clock shift (together with CCR2 = 00_H): 00_H
– 1-bit time-slot
Semiconductor Group
101