SAB82538 Datasheet, PDF (206/253 Pages) Infineon Technologies AG – ICs for Communications

EPT...
CON...
CRL...
CAPP...
CRCM...
PSD...
SAB 82538
SAF 82538
BISYNC Mode
Enable Preamble Transmission
This bit enables transmission of a preamble. The preamble is started after
Interframe Time Fill transmission has been stopped and a new block of data
is about to be transmitted. The preamble consists of an 8-bit pattern defined
via register PRE which is repeated a number of times selected by bits PRE0
and PRE1.
CRC ON
This bit determines whether the current data written to XFIFO has to be
included into CRC calculation or not. It has to be programmed before the
assigned byte/word is written to XFIFO. In the case of word access, both
characters are included. Since this control bit is copied in the XFIFO every
time a character is written, it is not necessary to reprogram it for each
character when consecutive characters are to be either all included into or
all excluded from CRC calculation.
0...data not included
1...data included.
CRC Reset Level
This bit defines the initialization for internal transmit CRC generator.
0...Initialized to “FFFF_H”.
1...Initialized to “0000_H”.
Note: The internal transmit CRC generator is automatically initialized
before transmission of a new frame starts.
CRC Append
If this bit is set, the internal transmit CRC generator is activated:
1. The CRC generator is initialized every time the transmission of a new
frame starts. Initialization value is defined via bit CRL.
2. During transmission all data with the CON bit set to “1” are included into
CRC checksum calculation.
3. The checksum is automatically appended to the last transmitted data of
the frame if a Transmit Message End command (XME) has been issued.
Select CRC Algorithm
Selects the CRC algorithm for the internal transmit CRC generator:
0...CRC-16 (X¹⁶ + X¹⁵ + X² + 1)
1...CRC-CCITT (X¹⁶ + X¹² + X⁵ + 1)
DPLL Phase Shift Disable
Only applicable in the case of NRZ and NRZI encoding.
If this bit is set to “1”, the Phase Shift function of the DPLL is disabled. In
this case the windows for Phase Adjustment are extended.
Semiconductor Group
206