SAB82538 Datasheet, PDF (66/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.3.3 SDLC Loop
As a special variant of IBM’s SDLC protocol the SDLC Loop is used to connect several
Secondary (= slave) Stations to one Primary (= master) Station. Different from standard
HDLC, a reserved bit sequence is defined as “End of Poll” sequence (EOP = one “0” bit,
followed by at least 7 “1” bits). Note that in standard HDLC this sequence is defined as
Abort Sequence, therefore with SDLC Loop frame abortion is not available.
The ESCC8 facilitates entering and leaving the loop. In contrast to the protocol support
described above, autonomous processing of S- and I-frames is not implemented by the
circuit but is left to software. Prerequisite for correct operation is
q SDLC Loop mode enabled (register CCR0)
q Normal Response Mode selected (XBCH:NRM = 1)
q Non-auto-mode or transparent mode with 8-bit address field selected
q External timer mode
q NRZ or NRZI data encoding enabled (register CCR0); no bus configuration
q R×CLK = T×CLK
q Interframe Timefill = Flags
Figure 31
SDLC Loop
The loop is formed by connecting T×D output of one station to the R×D input of the next
one (refer to figure 31). This configuration is physically a loop, but logically a point-to-
multipoint configuration.
In every Secondary Station data flow from R×D to T×D is handled depending on
Secondary’s current state as follows:
q Initially, RxD and TxD are connected together with gate delay (OFF Loop state). Data
sent out from the Primary is passed on by every Secondary to the next one. Thus, data
is transparent to all Secondaries.
Semiconductor Group
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