SAB82538 Datasheet, PDF (192/253 Pages) Infineon Technologies AG – ICs for Communications

CEC…
CTS…
SAB 82538
SAF 82538
BISYNC Mode
Command Executing
0… no command is currently executed, the CMDR register can be written
to.
1… a command (written previously to CMDR) is currently executed, no
further command can be temporarily written in CMDR register.
Note: CEC will be active at most 2.5 transmit clock periods. If the ESCC8
is in power down mode CEC will stay active.
Clear To Send State
This bit indicates the state of the CTS pin.
0… CTS is inactive (high)
1… CTS is active (low)
Command Register (WRITE)
Value after RESET: 00_H
7
CMDR RMC RRES RFRD STI
0
XF HUNT XME XRES (offset: 20)
Note: The maximum time between writing to the CMDR register and the execution of
the command is 2.5 clock cycles. Therefore, if the CPU operates with a very high
clock rate in comparison with the ESCC8’s clock, it is recommended that the CEC
bit of the STAR register be checked before writing to the CMDR register to avoid
any loss of commands.
RMC…
Receive Message Complete
Confirmation from CPU to ESCC8 that the current data block has been
fetched following a RPF or TCD interrupt or following a user initiated read
access in conjunction with the RFIFO Read command RFRD; the occupied
space in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after a TCD interrupt
in order to enable the generation of further receiver DMA requests.
RRES…
Receiver Reset
All data in RFIFO and BISYNC receiver is deleted.
Semiconductor Group
192