SAB82538 Datasheet, PDF (72/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.3.4.10 Receive Address Handling (version 2 upward)
Mask for Address Detection
The Receive Address Low/High Byte (RAL1/RAH1) can be masked by setting the
corresponding bits in the mask registers (AML/AMH) to allow extended broadcast
address recognition. This feature is applicable to all operating modes with address
recognition (auto mode, non-auto mode and transparent mode 1). It is disabled if all bits
of registers AML and AMH are set to zero (RESET value). The function of RAL2/RAH2
and detection of the fixed group address FEH or FCH if applicable to the selected
operating mode remain unchanged.
Note: As a very useful option, the detected receive address can be pushed to RFIFO
(CCR3.RADD).
Receive Address Pushed to RFIFO
As an option in the auto mode, non-auto mode and transparent mode 1, the address field
of received frames can be pushed to RFIFO (first one/two bytes of the frame). This
function is especially useful in conjunction with the extended broadcast address
recognition. It is enabled by setting control bit CCR3.RADD.
Note: In this case the ratio of receive frequency (fr) to transmit frequency (fx) and to
master clock frequency (fm) must fulfill:
fr/fx < 1.5 (normal operation),
fr/fm < 1.5 (master clock operation).
Semiconductor Group
72