SAB82538 Datasheet, PDF (215/253 Pages) Infineon Technologies AG – ICs for Communications

XDU...
TIN...
CSC...
XMR...
XPR...
SAB 82538
SAF 82538
BISYNC Mode
Transmit Data Underrun
A block of data in transmission has been terminated with IDLE, because the
XFIFO contains no further data.
Note: Transmitter and XFIFO are reset and deactivated if this condition
occurs. They are re-activated not before this interrupt status register has
been read. Thus, XDU should not be masked via register IMR1.
Timer Interrupt
The internal timer has expired (see also description of TIMR register).
Clear To Send Status Change
Indicates that a state transition has occurred on CTS. The actual state of
CTS can be read from STAR register (CTS bit).
Transmit Message Repeat
The transmission of the last block of characters has to be repeated because
- a collision has occurred when transmitting a character in a bus
configuration, or
- CTS (transmission enable) has been withdrawn during transmission of a
character in point-to-point configuration.
Transmit Pool Ready
A data block of up to 32 bytes can be written to XFIFO.
Interrupt Mask Register 0, 1 (WRITE)
Value after RESET: FF_H, FF_H
7
0
IMR0
TCD 1 PERR SCD PLLA CDSC RFO RPF (offset: 3A)
IMR1
1
1 ALLS XDU TIN CSC XMR XPR (offset: 3B)
Note: Unused bits have to be set to logical “1”.
Each interrupt source can generate an interrupt signal at port INT (function of the output
stage is defined via register IPC). A “1” in a bit position of IMR0 or IMR1 sets the mask
active for the interrupt status in ISR0 or ISR1. Masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are they visible in register GIS.
Moreover, they will
– not be displayed in the Interrupt Status Register if bit IPC.VIS is set to “0”
– be displayed in the Interrupt Status Register if bit IPC.VIS is set to “1”
Note: After RESET, all interrupts are disabled.
Semiconductor Group
215