SAB82538 Datasheet, PDF (203/253 Pages) Infineon Technologies AG – ICs for Communications

Channel Configuration Register 1 (READ/WRITE)
Value after RESET: 00_H
7
CCR1
0
0
0 ODS ITF CM2
SAB 82538
SAF 82538
BISYNC Mode
0
CM0 (offset: 2D)
Note: Unused bits have to be set to logical “0”.
ODS…
Output Driver Select
Defines the function of the transmit data pins (T×DA, T×DB)
0… T×D pin is an open drain output.
1… T×D pin is a push-pull output.
ITF...
Interframe Time Fill Format
Determines the idle (= no data to send) state of the transmit data pin (T×D)
0...Continuous logical “1” is output.
1...Continuous SYN characters are output.
CM2– CM0… Clock Mode
Selects one of 8 different clock modes:
000 clock mode 0
•
•
•
•
•
•
111 clock mode 7
Note: Clock mode 5 is only specified for version SAB 82538H-10, not for
SAB 82538H.
Semiconductor Group
203