SAB82538 Datasheet, PDF (147/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
In case an XMR interrupt has occured, an ALLS interrupt is
generated one clock period later automatically.
XPR...
Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO. XPR
enables the fastest access to XFIFO. It has to be used for transmission of
long frames, back-to-back frames or frames with shared flags. However,
starting transmission of a new frame should be initiated after ALLS interrupt
instead of XPR
– in auto mode
– in bus configurations
– if contents of XFIFO have to be unique, e.g. for automatic repetition of the
last frame in case of bus collisions or CTS control
(see also XMR interrupt).
Note: It is not possible to send transparent, or I-frames when a XMR or XDU interrupt
remains unacknowledged.
Interrupt Mask Register 0, 1 (WRITE)
Value after RESET: FF_H, FF_H
7
0
IMR0
RME RFS RSC PCE PLLA CDSC RFO RPF (offset: 3A)
IMR1
EOP OLP/ AOLP/ XDU/ TIN CSC XMR XPR (offset: 3B)
RDO ALLS EXE
Each interrupt source can generate an interrupt signal at port INT (characteristics of the
output stage are defined via register IPC). A “1” in a bit position of IMR0 or IMR1 sets
the mask active for the interrupt status in ISR0 or ISR1. Masked interrupt statuses
neither generate an interrupt vector or a signal on INT, nor are they visible in register
GIS. Moreover, they will
– not be displayed in the Interrupt Status Register if bit IPC.VIS is set to “0”
– be displayed in the Interrupt Status Register if bit IPC.VIS is set to “1”.
Note: After RESET, all interrupts are disabled.
Semiconductor Group
147