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SAB82538 Datasheet, PDF (243/253 Pages) Infineon Technologies AG – ICs for Communications
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SAB 82538
SAF 82538
Receive Cycle Timing
Parameter
No. Symbol
Limit Values
Unit
H
H-10
min. max. min. max.
Receive data rate
ext. clocked (except
ASYNC, BCR = 16)
2
10 Mbit/s
int. clocked
(HDLC, BISYNC:
only DPLL)
2
2
Mbit/s
int. clocked
(all other internal modes)
2
2
Mbit/s
Clock period
ext. clocked (except
67 tc(XC)
480
100
ns
ASYNC, BCR = 16)
int. clocked
(HDLC, BISYNC:
only DPLL)
480
480
ns
int. clocked
(all other internal modes)
480
480
ns
Receive data setup
Receive data hold
Carrier detect setup
Carrier detect hold
CD status change to INT
delay
t 68
su(RxD)
10
10
ns
69 th(RxD)
30
30
ns
70 tsu(CD)
50
50
ns
71 th(CD)
30
30
ns
72 tCD-INT
T73
T73 ns
+ 60
+ 60
Semiconductor Group
243
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