SAB82538 Datasheet, PDF (150/253 Pages) Infineon Technologies AG – ICs for Communications

Port Interrupt Mask Register Port A...D (WRITE)
Value after RESET: FF_H
7
PIMA
PIM7
SAB 82538
SAF 82538
HDLC Mode
0
PIM0 (03D/07D)
PIMB
PIM7
PIM0 (0BD/0FD)
PIMC
PIM7
PIM0 (13D/17D)
PIMD
0
0
0
0 PIM3
PIM0 (1BD/1FD)
Note: Unused bits have to be set to logical “0”.
Each PIM register is accessible via two channel addresses.
Each of the above bits is assigned to the corresponding Universal Port pin and to the bits
of register PIS with the same number (e.g. PIMA0 to pin PA0).
0… Interrupt source is enabled.
1… Interrupt source is disabled.
A “1” in a bit position of PIM sets the mask active for the interrupt status in PIS. Masked
interrupt statuses neither generate an interrupt vector or a signal on INT, nor are they
visible in register GIS.
Moreover, they will
– not be displayed in the Interrupt Status Register if bit IPC.VIS is set to “0”
– be displayed in the Interrupt Status Register if bit IPC.VIS is set to “1”.
Refer to description of register PIS.
Note: After RESET, all interrupt sources are disabled.
Semiconductor Group
150