SAB82538 Datasheet, PDF (180/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Interrupt Status Register 0 (READ)
Value after RESET: 00_H
7
ASYNC Mode
0
ISR0
TCD TIME PERR FERR PLLA CDSC RFO RPF (offset: 3A)
All bits are reset when ISR0 is read. Additionally, TCD and RPF are reset when the
corresponding interrupt vector is output.
Note: If bit IPC.VIS is set to “1”, interrupt statuses in ISR0 may be flagged although
they are masked via register IMR0. However, these masked interrupt statuses
neither generate an interrupt vector or a signal on INT, nor are visible in register
GIS.
TCD…
Termination Character Detected
The termination character (TCR) has been received or the execution of the
RFRD command issued before has been completed. A data block is now
available in the RFIFO. The actual block length can be determined by
reading register RBCL first.
TIME…
Time OUT
The time-out limit has been exceeded.
If the respective mask bit is reset (i.e. TIME interrupt is enabled), the
received data stream is monitored for exceeding the fixed time limit after the
last character has been received (time limit = 4 × CFL; character frame
length CFL includes start bit, character length, parity bit and stop bits).
PERR…
Parity Error
Only valid if parity check/generation is enabled.
If set, a character with parity error has been received. If enabled via RFDF,
parity error information is stored in RFIFO in the status byte pertaining to
that character.
FERR…
Framing Error
This bit indicates that a character has been received with a framing error,
i.e. the receiver has detected a “0” in a stop bit position. If enabled via
RFDF, this information is stored in RFIFO in the status byte pertaining to
that character.
Semiconductor Group
180