SAB82538 Datasheet, PDF (145/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Interrupt Status Register 1 (READ)
7
HDLC Mode
0
ISR1
EOP OLP/ AOLP/ XDU/ TIN CSC XMR XPR (offset: 3B)
RDO ALLS EXE
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC.VIS is set to “1”, interrupt statuses in ISR1 may be flagged although they
are masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
EOP...
End of Poll Sequence Detected
Only valid if SDLC Loop mode is selected.
It is set if an EOP sequence has been received.
OLP/RDO... On Loop
Only valid if SDLC Loop mode is selected.
It is set in response to a Go On Loop command, but not before an EOP
sequence has been received. It is also set when returning from the Active
On Loop state. All incoming bits on R × D are reflected onto T × D with one
bit delay.
Receive Data Overflow
Not applicable in SDLC Loop mode
This interrupt status is an early warning that data has been lost. It is
classified as group 7 or group 8 interrupt. Even when this interrupt status is
generated, the frame continues to be received when space in the RFIFO is
available again.
Note: Whereas the bit RSTA.RDO in the frame status byte indicates
whether an overflow occurred when receiving the frame currently accessed
in the RFIFO, the ISR1.RDO interrupt status is generated as soon as an
overflow occurs and does not necessarily pertain to the frame currently
accessed by the processor or the DMA controller.
AOLP/ALLS... Active On Loop
Only valid if SDLC Loop mode is selected.
It is set in response to a Go Active On Loop command, but not before an
EOP sequence has been received. T × D is disconnected from R × D and
transmission of Flags or data is started.
All Sent
Only valid if SDLC loop mode is not selected.
Semiconductor Group
145