SAB82538 Datasheet, PDF (226/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Figure 56
Siemens/Intel Write Cycle Timing
Note 1: Function of DTACK is described logically as:
DTACK = (CS x DACK + RD x WR) x INTAi
INTAi is an internally generated signal.
Note 2: DRT is reset with the falling edge of CS or DACK if the last write access to
XFIFO is expected. However, DRT will be activated again in the case of an
access to any other register or FIFO.
Semiconductor Group
226