SAB82538 Datasheet, PDF (159/253 Pages) Infineon Technologies AG – ICs for Communications

XRES…
SAB 82538
SAF 82538
ASYNC Mode
memory to ESCC8 by DMA. Serial data transmission starts as soon as
32 bytes/16 words are stored in the XFIFO or the Transmit Byte Counter
value is reached.
Transmitter Reset
XFIFO is cleared of any data and IDLE (logical “1s”) is transmitted. This
command can be used by the CPU to abort current data transmission. In
response to XRES an XPR interrupt is generated.
Mode Register (READ/WRITE)
Value after RESET: 00_H
7
0
MODE
0
0
0 FLON RAC RTS TRS TLP (offset: 22)
Note: Unused bits have to be set to logical “0”.
FLON…
Flow Control ON
The in-band flow control is activated via this bit:
0… No further action is automatically taken by the ESCC8. However,
recognition of an XON or an XOFF character (defined via registers
XON and XOFF) causes always a corresponding maskable interrupt
status to be generated (refer to register ISR1).
1… The reception of an XOFF character (defined via register XOFF)
automatically turns off the transmitter after the currently transmitted
character (if any) has been completely shifted out (XOFF state). The
reception of an XON character (defined via register XON)
automatically makes the transmitter resume transmitting (XON state).
RAC…
Receiver Active
Switches the receiver to operational or inoperational state.
0… receiver inactive
1… receiver active
Semiconductor Group
159