SAB82538 Datasheet, PDF (19/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Pin Definitions and Function (cont’d)
Pin No. Symbol
Input (I) Function
Output (O)
41
RTS0
O
42
RTS1
43
RTS2
44
RTS3
45
RTS4
46
RTS5
47
RTS6
48
RTS7
Request to Send (Channel 0 … 7)
When the RTS bit in the MODE register is set, the
RTS signal goes low. When the RTS bit is reset,
the signal goes high if the transmitter has finished
and there is no further request for a transmission.
In bus configuration, RTS can be programmed via
CCR2 to:
– go low during the actual transmission of a
frame shifted by one clock period, excluding
collision bits.
– go low during reception of a data frame.
– stay always high (RTS disabled).
134
CTS0/CxD0 I
133
CTS1/CxD1
132
CTS2/CxD2
131
CTS3/CxD3
130
CTS4/CxD4
129
CTS5/CxD5
128
CTS6/CxD6
127
CTS7/CxD7
Clear to Send (Channel 0 … 7)
A low on the CTSn input enables the respective
transmitter. Additionally, an interrupt may be
issued if a state transition occurs at the CTSn pin
(programmable feature).
If no “Clear To Send” function is required, the
CTSn inputs can be directly connected to GND.
Collision Data (Channel 0 … 7)
In a bus configuration, the external serial bus
must be connected to the corresponding C×D pin
for collision detection.
126
CD0
I
125
CD1
124
CD2
123
CD3
122
CD4
121
CD5
120
CD6
119
CD7
Carrier Detect (Channel 0 … 7)
The function of this pin depends on the selected
clock mode. It can supply:
– either a modem control or a general purpose
input (clock modes 0,2,3,4,6,7). If auto-start is
programmed, it functions as a receiver enable
signal.
– or a receive strobe signal (clockmode 1).
– or a frame synchronization signal in time-slot
oriented operation mode (clock mode 5).
Additionally, an interrupt may be issued if a state
transition occurs at the CDn pin (programmable
feature).
Semiconductor Group
19