SAB82538 Datasheet, PDF (124/253 Pages) Infineon Technologies AG – ICs for Communications

Receive Address Byte High Register 1 (WRITE)
7
RAH1
RAH1
SAB 82538
SAF 82538
HDLC Mode
0
CRI 0 (offset: 26)
In operating modes that provide high byte address recognition, the high byte of the
received address is compared with the individually programmable values in RAH1 and
RAH2.
In versions 2 and upwards, this register can be masked by setting the corresponding bits
in the mask register AMH to allow extended broadcast address recognition. This feature
is applicable to all operating modes with address recognition.
RAH1… Value of the first individual high address byte
CRI…
Command/Response Interpretation
The setting of the CRI bit affects the meaning of the C/R bit in RSTA as
follows:
C/R Meaning
C/R
Value
Commands received
0
1
Responses received
1
0
CRI = 1
CRI = 0
Important Note: If 1-byte address field is selected in auto-mode, RAH1
must be set to 00_H.
Semiconductor Group
124