SAB82538 Datasheet, PDF (92/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.6.3.2 Collisions
During the transmission, the data transmitted on T×D is compared with the data on C×D.
In case of a mismatch (1 sent and 0 detected, or vice versa) data transmission is
immediately aborted, and idle (logical 1) is transmitted.
HDLC/SDLC: Transmission will be initiated again by the ESCC8 as soon as possible if
the first part of the frame is still present in the XFIFO. If not, an XMR interrupt is
generated.
Since a zero (“low”) on the bus prevails over a 1 (high impedance) if a wired-or
connection is implemented, and since the address fields of the HDLC frames sent by
different stations normally differ from one another, the fact that a collision has occurred
will be detected prior to or at the latest within the address field. The frame of the
transmitter with the highest temporary priority (determined by the address field) is not
affected and is transmitted successfully. All other stations cease transmission
immediately and return to bus monitoring state.
BISYNC: Transmitter and XFIFO are reset and pin T×D goes to “1”. The XMR interrupt
is provided which requests the microprocessor to repeat the whole message or block of
characters.
ASYNC: Bus configuration not recommended.
Note: If a wired OR connection has been realized by an external pull-up resistor without
decoupling, the data output (T×D) can be used as an open drain output and
connected directly to the C×D input.
For correct identification as to which frame is aborted and thus has to be repeated
after an XMR interrupt has occurred, the contents of XFIFO have to be unique,
i.e. XFIFO should not contain data of more than one frame as it could happen
when servicing is done after an XPR interrupt. For this purpose the All Sent
interrupt (ISR1.ALLS) instead of XPR has to be used to trigger the loading of data
(for the next frame) into XFIFO.
Semiconductor Group
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