SAB82538 Datasheet, PDF (106/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
ASYNC: The transmission of character(s) can be started by issuing a XF command via
the CMDR register. The ESCC8 will repeatedly request for the next data block by means
of a XPR interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a
32-byte pool is accessible to the CPU. Transmission may be aborted per software
(CMDR.XRES).
BISYNC: The transmission of a block can be started by issuing a XF command via the
CMDR register. Further handling of data transmission with respect to preamble
transmission and command XME is similar to HDLC/SDLC mode. After XME command
has been issued, the block is finished by appending the internally generated CRC if
enabled (refer to description of register CCR3).
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the block is terminated with IDLE and the CPU is notified per interrupt
(ISR1.XDU). The block may also be aborted per software (CMDR.XRES). The data
transmission flow, from the CPU’s point of view, is outlined in figure 44.
Figure 44
Interrupt Driven Data Transmission (Flow Diagram)
Semiconductor Group
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