SAB82538 Datasheet, PDF (38/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.2.2 Data Transfer Modes
Data transfer between the system memory and the ESCC8 for all eight channels is
controlled by either interrupts (Interrupt Mode), or independently from CPU, using the
ESCC8's 16-channel DMA interface (DMA Mode).
After RESET, the ESCC8 operates in Interrupt Mode, where data transfer must be done
by the CPU. The user selects the DMA Mode by setting the DMA bit in the XBCH
register. All eight channels can be independently operated in either Interrupt or DMA
Mode.
2.2.3 Interrupt Interface
Special events in the ESCC8 are indicated by means of a single interrupt output with
programmable characteristics (open drain, push-pull; IPC register), which requests the
CPU to read status information from the ESCC8, or, if Interrupt Mode is selected, to
transfer data from/to ESCC8.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the CPU
q By evaluating the interrupt vector which is generated by ESCC8 during an interrupt
acknowledge cycle (Note: For version 2 upward the format of the interrupt vector is
changed to separate parallel port interrupts from channel assigned interrupts), and/or
q By reading the ESCC8's interrupt status registers (GIS, ISR0, ISR1, PIS).
Semiconductor Group
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