SAB82538 Datasheet, PDF (112/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
4
Detailed Register Description
In the register description the register addresses are specified by an “offset” relative to
the “base addresses”, which are 000, 040, 080, 0C0, 100, 140, 180, 1C0 for the eight
channels, respectively.
4.1 Status/Control Registers in HDLC Mode
4.1.1 Register Addresses
Table 9
Register Addresses in HDLC Mode
Address (A8 … A0)
Channel
0
1
2
3
4
5
6
7
000 040 080 0C0 100 140 180 1C0
……………………
01F 05F 9F 0DF 11F 15F 19F 1DF
020 060 0A0 0E0 120 160 1A0 1E0
021 061 0A1 0E1 121 161 1A1 1E1
022 062 0A2 0E2 122 162 1A2 1E2
023 063 0A3 0E3 123 163 1A3 1E3
024 064 0A4 0E4 124 164 1A4 1E4
025 065 0A5 0E5 125 165 1A5 1E5
026 066 0A6 0E6 126 166 1A6 1E6
027 067 0A7 0E7 127 167 1A7 1E7
028 068 0A8 0E8 128 168 1A8 1E8
029 069 0A9 0E9 129 169 1A9 1E9
02A 06A 0AA 0EA 12A 16A 1AA 1EA
02B 06B 0AB 0EB 12B 16B 1AB 1EB
02C 06C 0AC 0EC 12C 16C 1AC 1EC
02D 06D 0AD 0ED 12D 16D 1AD 1ED
02E 06E 0AE 0EE 12E 16E 1AE 1EE
02F 06F 0AF 0EF 12F 16F 1AF 1EF
030 070 0B0 0F0 130 170 1B0 1F0
031 071 0B1 0F1 131 171 1B1 1F1
032 072 0B2 0F2 132 172 1B2 1F2
033 073 0B3 0F3 133 173 1B3 1F3
034 074 0B4 0F4 134 174 1B4 1F4
035 075 0B5 0F5 135 175 1B5 1F5
Register
Read
Write
RFIFO
XFIFO
STAR
CMDR
RSTA
PRE
MODE
TIMR
XAD1
XAD2
———
RAH1
———
RAH2
RAL1
RHCR
RAL2
RBCL
XBCL
RBCH
XBCH
CCR0
CCR1
CCR2
CCR3
———
TSAX
———
TSAR
———
XCCR
———
RCCR
VSTR
BGR
———
RLCR
Semiconductor Group
112