SAB82538 Datasheet, PDF (130/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Channel Configuration Register 0 (READ/WRITE)
Value after RESET: 00_H
7
HDLC Mode
0
CCR0
PU MCE 0 SC2 SC1 SC0 SM1 SM0 (offset: 2C)
Note: Unused bits have to be set to logical “0”.
PU…
Switches between power up and power down mode
0… power down (standby)
1… power up (active)
MCE…
Master Clock Enable
If this bit is set to “1”, the clock provided via pin XTAL1 works as master
clock to allow full functionality of the microprocessor interface (access to all
status and control registers and FIFOs, DMA and interrupt support)
independent of the receive and the transmit clocks. The internal oscillator
in conjunction with a crystal on XTAL1-2 can be used, too. The master clock
option is not applicable in clock mode 5 or in SDLC Loop mode. Refer to
table 5 for more details.
Note: The internal timers run with the master clock.
SC2 – SC0… Serial Port Configuration
000… NRZ data encoding
001… bus configuration, timing mode 1
010… NRZI data encoding
011… bus configuration, timing mode 2
100… FM0 data encoding
101… FM1 data encoding
110… MANCHESTER data encoding
111… (not used)
Note: If bus configuration is selected, only NRZ coding is supported.
SM1 – SM0… Serial Mode
00… HDLC/SDLC mode
01… SDLC Loop mode
10… BISYNC mode
11… ASYNC mode
Semiconductor Group
130