SAB82538 Datasheet, PDF (49/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.2.4 DMA Interface
The ESCC8 comprises a 16-channel DMA interface for fast and efficient data transfers.
For all serial channels, a separate DMA Request output for transmit (DRT) and receive
direction (DRR) as well as a DMA Acknowledgement (DACK) input is provided.
The ESCC8 activates the DMA Request line as long as data transfers are needed from/
to the specific FIFO (level triggered demand transfer mode of DMA controller).
It is the responsibility of the DMA controller to perform the correct amount of bus cycles.
Either read cycles will be performed if the DMA transfer has been requested from the
receiver, or write cycles if DMA has been requested from the transmitter. If the DMA
controller provides a DMA acknowledge signal (input to the ESCC8’s DACK pin), each
bus cycle implicitly selects the top of the specific FIFO and neither address (via A1-A8)
nor chip select need to be supplied (I/O to Memory transfers). If no DACK signal is
supplied, normal read/write operations (with addresses) must be performed (Memory to
Memory transfers). The ESCC8 deactivates the DMA Request line immediately after the
last read/write cycle of the data transfer has started.
As a very useful feature for single cycle DMA transfers, optional inversion of the
functions of read/write control lines is implemented. If programmed via register CCR2
– RD and WR are exchanged in Intel bus interface mode,
– R/W is inverted in Motorola bus interface mode
while DACK is active. This allows easy connection to DMA controllers without dedicated
I/O control lines as shown in figure 16.
Figure 16
DMA Interfacing by Using Invert Mode
Semiconductor Group
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